I am an Analog/Mixed-Signal IC Designer with hands-on experience in circuit design across 28 nm–180 nm technologies, including tapeout experience with open-source PDKs such as SKY130, GF180MCU, and IHP SG13G2 (130 nm BiCMOS). I worked as a Research Intern at the LP-CAS (Low-Power Circuits and Systems) Lab, IIT Gandhinagar, under the guidance of Prof. Madhav K. Pathak, where I worked on ring amplifiers and their applications in low-power LDOs. I am currently working in industry on PVT Monitor and Reference IPs in 28 nm CMOS.
These experiences have helped me develop a strong interest in energy-efficient circuit design, research-driven problem solving, and translating circuit-level ideas into practical systems and applications.
Research InterestsI am particularly interested in energy-efficient analog and mixed-signal circuits for sensing, computation, and data conversion, and in co-designing circuits and algorithms for emerging computing architectures.
I hope to build practical circuit and system-level technologies with real-world impact, especially in healthcare, therapy, sensing, and assistive technologies, where integrated circuits can help improve people's lives.
I am also an IEEE SSCS Code-a-Chip Travel Grant Recipient for ESSERC 2026, where I presented my work on Ron/gm based design methodology for dynamic amplifiers.
I am actively seeking PhD positions for Fall 2027.
Block Designs: Designed the Bandgap Core and Reference Analog blocks for the PVT Monitor and Reference IPs in TSMC 28 nm CMOS.
Block Designs: Designed a 4-input PWM comparator with programmable hysteresis for a multi-phase DC-DC converter SoC in UMC 55 nm CMOS.
Block Designs: Dynamic Amplifiers and Ring Amplifier-based LDO at LP-CAS Lab, IITGN.
Tapeout: Designed a piecewise-compensated, high-PSRR Bandgap Reference with sub-5 ppm/°C TC in SKY130, including a low-power always-on startup circuit; fabricated through the TinyTapeout SKY130 shuttle.
GeoSat-based satellite communication in the Antenna System for Satellite TTC within C-Band (6 GHz) at the Baseband RF Division, Master Control Facility. Calibrated antenna systems to achieve Cross-Polar Discrimination (XPD) during In-Orbit Testing of GSAT-31.
Visvesvaraya Technological University · Bengaluru, India
CGPA8.6/ 10
Select a node to explore how skills, places, and outputs connect.
Conference papers, magazine features, and presentations.
IEEE SSCS Magazine · Dec 2026
IEEE SSCS Magazine: Ron/gm based design methodology featured within the IEEE SSCS magazine on code a chip competition.
Nithin P, Pramoda SR, Suyajnaa, Runpeng Gao, Praveen Kumar Venkatachala, and Madhav Pathak, “Ron/gm based design methodology for dynamic amplifiers,” IEEE Solid-State Circuits Magazine, Dec. 2026, to appear.
@article{p2026rongm,
author = {Nithin P and Pramoda SR and Suyajnaa and Runpeng Gao and Praveen Kumar Venkatachala and Madhav Pathak},
title = {{$R_{on}/g_m$} Based Design Methodology for Dynamic Amplifiers},
journal = {IEEE Solid-State Circuits Magazine},
year = {2026},
month = dec,
note = {To appear}
} 
IEEE ICEE 2025 · Feb 2025
Design and comparison of analog multiplier circuits for low-power pre-ADC sensor processing, power management, and analog neural networks using translinear and linear MOSFET-based MAC architectures.
Nithin P and Madhav Pathak, “Analog CMOS multiplier circuits: design and comparative analysis,” in IEEE ICEE 2025, Feb. 2025.
@inproceedings{p2025multiplier,
author = {Nithin P and Madhav Pathak},
title = {Analog {CMOS} Multiplier Circuits: Design and Comparative Analysis},
booktitle = {IEEE ICEE 2025},
year = {2025},
month = feb,
url = {https://ieeexplore.ieee.org/abstract/document/11409824}
} 
ESSERC 2026 · Palma de Mallorca, Spain · Sept 2026
Recipient of the IEEE SSCS Code-a-Chip Travel Grant Award. Presented the work on a Ron/gm-based design methodology for dynamic amplifiers at the award ceremony.
Nithin P, Pramoda SR, Suyajnaa, Runpeng Gao, Praveen Kumar Venkatachala, and Madhav Pathak, “Ron/gm based design methodology for dynamic amplifiers,” presented at ESSERC 2026, Palma de Mallorca, Spain, Sep. 2026.
@misc{p2026rongmesserc,
author = {Nithin P and Pramoda SR and Suyajnaa and Runpeng Gao and Praveen Kumar Venkatachala and Madhav Pathak},
title = {{$R_{on}/g_m$} Based Design Methodology for Dynamic Amplifiers},
howpublished = {Presentation at ESSERC 2026 (IEEE SSCS Code-a-Chip Travel Grant), Palma de Mallorca, Spain},
year = {2026},
month = sep,
url = {https://colab.research.google.com/drive/1q6r7tg8RoyLBaMS3b7EONwkPCBzEM2c1}
} 
IEEE Solid-State Circuits Society (SSCS) – Open-Source Ecosystem (TC-OSE)
Grant$5,000
Awarded for “Ron/gm Based Design Methodology for Dynamic Amplifiers”, a notebook demonstrating a novel design methodology for inverter-based dynamic amplifiers on IHP SG13G2 using open-source EDA tools. Award ceremony at ESSERC 2026, Palma de Mallorca, Spain.
Dynamic amplifiers exhibit two distinct settling regimes: an initial non-linear, large-signal phase dominated by the transistor on-resistance Ron, followed by a linear, small-signal phase governed by gm. During the first phase, the output rapidly moves toward its final value with an effective time constant
τLS ≈ RonCload,
while the final settling and small-signal bandwidth are determined by
τSS ≈ Cload / gm.
Conventional gm/ID-based design methods are effective for small-signal optimization, but do not directly constrain signal-dependent Ron, required voltage swing, or the resulting large-signal settling behavior. Consequently, a design with sufficient gm at nominal conditions can still exhibit slow settling at process corners where Ron increases.
We therefore propose a Ron/gm-based design methodology that explicitly allocates the settling-time budget between the two regimes. For a target settling time Tsettle, a fraction α is assigned to small-signal settling and (1 − α) to large-signal settling:
Ron = (1 − α)Tsettle / 5Cload , gm,min = 5Cload / α Tsettle.
The required gm is then selected as the larger of the settling requirement and the application bandwidth requirement,
gm = max( gm,min , 2π fBWCload ).
This provides a direct connection between Ron, gm, Cload, bandwidth, and settling time, allowing the unit cell to be sized independently of the final load and subsequently scaled by a multiplier M:
Ron → Runit / M , gm → M gm,unit , ID → M ID,unit.
Importantly, the proposed approach separates the two design knobs. The signal-path transistor width is primarily fixed by the required Ron, while gm can be further tuned through a replica bias path by adjusting its current and device sizing across process corners. This allows small-signal bandwidth to be corrected without altering the signal-path Ron and therefore without compromising large-signal settling.
The resulting Ron/gm metric provides a pre-simulation design and corner-verification framework for dynamic amplifiers, exposing slow-corner settling mechanisms that can remain hidden in a conventional gm/ID-only design flow.
expand | Design Criterion | Ron/gm (This Work) | gm/ID Methodology | Conrad et al. [TCAS-I 2020] |
|---|---|---|---|
| I. METHODOLOGY | |||
| Design paradigm | Analytical LUT Physics-based; pre-characterised | Analytical LUT Small-signal only | Simulation-based numerical optimizer Cadence ADE XL |
| Primary design parameter | Ron/gm Couples large-signal + small-signal | gm/ID Small-signal only | ma1, ma2, ma3, Ibias, R, Caz 6 numerical params; no physical link |
| Design entry stage | Pre-simulation | Pre-simulation Partial - no large-signal info | Requires full transient simulation per iteration |
| II. SETTLING PHASE COVERAGE | |||
| Non-linear (large-signal / RC) settling characterized | Via Ron in LUT; τls = RonCL | Ron absent from gm/ID framework | Acknowledged as "not practical" [4]† |
| Small-signal (gm C) settling characterized | Via gm,bias in LUT; BW = gm/(2π CL) | Primary strength of gm/ID methodology | Via rms error cost function |
| Unified two-phase settling model | Ron/gm co-constrains both τLS and τSS | Small-signal-phase only | No time-budget allocation between phases |
| Peak slew current Ipeak predicted pre-simulation | Ipeak ∝ 1/(Ron/gm); log-log scale slope = -1 | Post-optimization verification only | |
| III. PROCESS CORNER ROBUSTNESS | |||
| TT / SS / FF corners visible at design entry | All 3 corners in LUT; SS worst-case directly readable | LUT can be corner-swept but Ron not extracted | PVT excluded from optimizer loop‡ |
| Deadzone bias (VDZN, VDZP) determined pre-simulation | Per-corner, from Vbias vs Ron/gm plot§ | Unknown without iterative transient corner sweeps | Vos is one of 6 optimized params; corner sensitivity unknown a priori |
| SS-corner Ron degradation visible a priori | |||
| IV. DESIGN EQUATIONS AND PHYSICAL INSIGHT | |||
| Closed-form design equations available | Vbias = VTH + 2ID/gm; gm,bias ∝ (Ron/gm)-1/3; Ron/gm ∝ L2/(W ID) | For small-signal: Gm = 2π f CL; W = ID / (ID/W)|LUT | Stability criterion exists but "not realizable" as design equation† |
| Physical insight preserved throughout design | Every plot axis maps to a physical quantity | For small-signal operating point only | Optimizer returns numbers; no physical link retained |
| Subsumes gm/ID methodology | gm/ID readable from gm/ID vs Ron/gm plot; reverse not possible | – | |
| V. PRACTICAL DESIGN FLOW | |||
| EDA tool requirement | Open-source and Commercial tools Any spice + Python/Matlab | Spectre (LUT gen.) Helper usable standalone | Cadence Virtuoso + Spectre + ADE XL Full commercial license stack |
| Application-specific redesign required | LUT generated once per technology node | LUT reusable across applications | New testbench + cost function per application |
| Cost function calibration required | Manual ×4 adjustment applied in paper¶ | ||
| PVT robustness in design loop | SS/FF corner LUTs included by design | Corner LUT possible; dynamic behavior not covered | Excluded from optimizer; post-hoc Monte Carlo only‡ |
| Technology portability | 15 ngspice sims re-characterize any PDK (~1 min) | New Spectre LUT per node | Full optimizer rerun needed; 180 nm fails power target by 13×** |
| VI. DESIGN EXAMPLE RESULTS (IBA, Tsettle = 250 ns, UGB = 9.55 MHz (60 Mrad/s), CL,eff = 667 fF, IHP SG13G2 130 nm) | |||
| Gm target met (UGB = 9.55 MHz) | ≈ 40 μS | ≈ 40 μS | 15-bit ENOB |
| Ipeak range | 14 μA (pos edge), -13.86 μA (neg edge) | ||
| Ron known before transient simulation | 4 kΩ unit; 1 kΩ after ×4 multiplier | Post-simulation discovery only | |
| VDZN (NMOS deadzone) pre-simulation | FF: 0.355 V | TT: 0.390 V | SS: 0.425 V | ||
| VDZP (PMOS deadzone) pre-simulation | FF: 0.970 V | TT: 1.110 V | SS: 1.204 V | ||
| Extra transient sims needed to obtain VDZ and Ron | Zero | Multiple corner sweeps required | Full optimizer run per corner |
Pre-simulation Vbias predictions were within ±75 mV of post-simulation values; Ipeak predicted within ~15%.
† J. Conrad et al.: "Unfortunately, Section II-B is not really practical for designing a RAMP… This makes a design-by-equation cumbersome and not realizable." [TCAS-I 2020, Sec. II-C]
‡ J. Conrad et al.: "PVT variations are not encountered during the circuit optimization, because this would require many transient simulations to evaluate one iteration of the optimizer." [TCAS-I 2020, Sec. V-E]
§ Deadzone bias values read from the Vbias vs. log(Ron/gm) LUT plot at Ron/gm = 50 × 106 (per device, post-multiplier), Ibias = 0.5 μA (unit cell), Ibias = 2 μA (Overall IBA).
¶ J. Conrad et al.: "the optimizer goal for the accuracy was readjusted ×4 smaller, i.e. 0.25 for the cost function." [TCAS-I 2020, Sec. IV-B.3]
** J. Conrad et al., Table II: 180 nm power cost function = 12.99 (target: 1.0), failing the power constraint by 13×.
SKY130 · TinyTapeout · Bandgap reference
PCB - Lab testbench 1 
PCB - Lab testbench 2 GF180MCU-D · TinyTapeout · DRC / LVS / PEX
SKY130 · Power-on reset
Python · NGSpice · Magic VLSI
IHP SG13G2 · Ring amplifier
SKY130 · Subthreshold reference
SKY130 · LDO
SKY130 · Folded-cascode OTA
SKY130 · Fully differential OTA
Browser-based tools I built for my own work in circuit design, research and finance. All run entirely in your browser.
IHP SG13G2 · SKY130A · GF180MCU-D
Unified gm/ID explorer for three open-source PDKs: interactive MOSFET characterisation curves (gm/ID, fT, gm/gds and more versus VGS, Vov and channel length) for gm/ID-based analog design.
Semiconductor equities · in-browser analytics
Quantitative stock analytics for semiconductor professionals evaluating equity offers. Runs entirely in the browser.
Seven INR pairs · ECB reference rates
Quantitative analysis of seven INR currency pairs (EUR, USD, GBP, JPY, CNY, SGD, HKD) for timing a transfer: ensemble forecasts (ARIMA, Holt-Winters, Monte Carlo), technical indicators, risk and seasonality, on ECB rates refreshed daily by a data bot.
AI · Finance · Chip design
Live feed of the newest papers and posts in AI, finance and chip design: arXiv, Hugging Face trending papers, the latest IEEE JSSC, TCAS, TVLSI, TCAD and IEEE Micro articles, Semantic Scholar and research blogs, refreshed every 3 hours, with an optional Claude-powered paper explainer.
Analog · VLSI · CAS conferences
Tracks conference information such as submission deadlines, with a calendar feed and change log.
Delta-sigma ADC · SRAM PUF · NLFSR
Interactive signal-path explorer for a secure delta-sigma sensor front end, running a behavioural model live in the browser. Compares the ESSERC'25 S-DSM baseline with a proposed SRAM-PUF + fuzzy extractor + NLFSR scheme, and lets you probe every block, from the modulator bitstream to key recovery, under attack scenarios.
31 public repositories · 81 stars - more on GitHub.
Outside of circuit design, my primary interests lie in macroeconomics and data-driven quantitative analysis of businesses and financial markets, particularly the use of machine learning and large-scale economic and financial datasets to study economic trends, business decisions, and investment opportunities.
JavaScript · Semiconductor Equities · Monte Carlo · VaR/CVaR · Sharpe/Sortino
Python · ARIMA · Holt-Winters · SciPy
Applied ARIMA and Holt-Winters exponential smoothing models for financial time-series forecasting and trend decomposition.
Python · NumPy · Pandas · Scikit-learn
Implementation of standard risk metrics including Value-at-Risk (VaR), Conditional VaR (CVaR), Beta, Sharpe ratio, and Sortino ratio for portfolio performance evaluation.
Especially classical history and the Roman Empire.
Advaita Vedanta - the teaching of non-duality.
The goal: travel the world.
Need the latest version? Email me and I’ll send it directly.
I am seeking PhD positions for Fall 2027 in analog and mixed-signal IC design. Email is the best way to reach me.
